1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to scan testing of integrated circuits.
2. Background of Invention
Effective testing of integrated circuits significantly enhances the ability of integrated circuit developers and manufacturers to provide reliable devices. Various techniques have been employed to test integrated circuits during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex integrated circuit. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an integrated circuit function properly. The sheer number of flip-flops within an integrated circuit, which is often greater than a million, presents a daunting challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within integrated circuits that have been designed to support scan testing.
Typically, complex integrated circuits are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single integrated circuit.
One challenge to providing effective scan testing is ensuring that the contents of memory devices remain constant or are controlled during scan testing. When the contents of memory devices are not controlled during testing, memory outputs can cause the contents of flip-flops under scan testing to unexpectedly change leading to output patterns that do not correspond to reference patterns. To control the content of memory devices, clock signals input into the memory devices must be controlled.
Furthermore, as processor speeds have increased, controlling memory during scan testing has become more complicated. Circuitry to control the clock input during testing must not induce delays into the clock signal input path during normal operation. Even slight delays on the order of picoseconds can potentially lead to erratic behavior in an integrated circuit.
What is needed are circuits and methods of control of clock signals for memory devices to facilitate efficient scan testing without impairing the normal operation of an integrated circuit.